Phase-lock-loops (PLL) may utilize a phase detector for comparing the phase of a reference clock with that of an output clock that utilizes a voltage controlled oscillator (VCO) to generate a phase error that varies a control voltage on the input to the VCO. By adjusting this control voltage, the phase of the VCO can be locked to the phase of the reference clock. Typically, some type of loop filter is disposed between the phase detector and the VCO. Generally, the loop filter is used to perform the function of blocking off undesirable frequency from the incoming signals.
In a PLL system, a typical phase detector generates control voltages for controlling a charge pump circuit which is operable to selectively pump charge (UP current) to a node for increasing a voltage level or pulling charge (DOWN current) from the node to provide a decreasing voltage level. To increase the voltage level, charge is sourced from a supply and, to decrease the voltage level, charge is sinked to a ground reference. When the relative phase between the VCO and the reference clock are either lagging or leading, then either the sourcing or sinking of a charge pump is controlled.
Charge pumps may include two current sources that are switched to the voltage input of the VCO. When charge is being sourced to the node, the phase of the VCO will change from either a lagging or leading phase to a leading or lagging phase, such that the phase detector will then cause the charge pump to sink current. When the PLL is locked, the phase error should be substantially at a zero phase error, which should result in no current being sourced to or sinked from the voltage control input of the VCO.
A prior art charge pump 100 is illustrated in FIG. 1. The charge pump 100 includes a loop filter 102 that is constructed as an RC network. Specifically, the loop filter 102 includes a resistor 104 and a capacitor 106 in series, where the capacitor 106 has a terminal coupled to a reference potential. The resistor 104 and the capacitor 106 define the zero of the loop filter 102. The loop filter 102 further includes a capacitor 108 coupled in parallel with the resistor 104 and the capacitor 106. The loop filter 102 is coupled to a first output node 110 of the charge pump 100. The loop filter 102 is primarily implemented to suppress spikes, ringing and other noise that may influence a regulator 112 (discussed in the next paragraph) when the charge pump 100 handles input control voltages.
As indicated, the prior art charge pump 100 also includes the regulator 112, which is used to regulate a second output node 114 of the charge pump 100 to the same voltage at a node 116 of the loop filter 102. This is achieved by controlling a current source 120. A capacitor 118 is coupled to the second output node 114 and the regulator 112. Assuming appropriate component value selection, the capacitor 118 coupled with the capacitor 106 ensure the first output node 110 and the second output node 114 are in static balance with respect to one another.
Different types of transistors used by the charge pump 100 may cause asymmetric current (UP current and DOWN current) to be supplied to the loop filter 102. If this occurs, the same asymmetric current would also be supplied to the capacitor 118. This causes the regulator 112 compensate for this asymmetric behavior. Disturbances fed into the regulator 112 may disrupt the symmetry between the UP and DOWN current sources.